





Removal of Noise in Digital Image by Using Novel Architecture of Filter
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This paper introduces, a new intelligent hardware module suitable for the computation of an adaptive median filter is presented for the first time. The noise detection procedure can be controlled so that a range of pixel values is considered as impulse noise. In this way, the blurring of the image in process is avoided, and the integrity of edge and detail information is preserved. Experimental results with real images demonstrate the improved performance. The proposed digital hardware structure is capable to process gray-scale images of 8-bit resolution and is fully pipelined, whereas parallel processing is used in order to minimize computational time. In the presented design, a 3×3 or 5×5 pixel image neighborhood can be selected for the computation of the filter output. However, the system can be easily expanded to accommodate windows of larger sizes. The proposed digital structure was designed, compiled and simulated using the Modelsim and Synthesized in Xilinx.
Keywords
AMF, FPGA.
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