Design of FFT & IFFT Using Double-Precision Fused Floating Point Operations

Now a day's both FFT and it's Inverse has very wide application in high data rate wireless communication system. It use butterfly operations consist of multiplication, addition and subtraction of complex data. Two fused floating-point operations using 32-bit representation had been developed to minimize delay and space consumption of FFT. Though it reduces the area and delay it produces output with round-off errors, due to which the FFT's accuracy and throughput are degraded in single-precision representation. To overwhelm these inconveniences two Double-Precision fused floating-point operations are projected. The proposed architectures are Double-Precision Fused Addition and Subtraction (DPFAS) unit and Double-Precision Fused Dot-Product (DPFDP) unit. The floating-point fused add-subtract unit performs an addition and a subtraction in parallel on the same pair of data and fused dot product unit performs floating-point multiplication and addition operations on two pairs of data. If we tend to had additional bits to represent information in floating-point operations round-off errors would be reduced. So by representing the information in double-precision rather than single-precision can cut back round-off errors in order that we are able to improve the accuracy and turnout of the computation units.