Design Power Efficient 4:2 Compressor using Full Adder for Arithmetic Circuits

This paper is present the design of the 4:2 compressor using full adder cell. The compressor is used in many arithmetic designs in the DSP system. Here the lower orders compressor are used to design the system which gives the better performance in the circuits .The inexact and approximate adders are used to overcome the complexity of the various VLSI circuits. Most of arithmetic design use multiplier and adder to reduce the complexity, by reducing the number of transistor we can reduce the area, the power consumption in circuit and also overcome the delay. In this paper lower order Compressor are used. The conventional digital computation arithmetic circuits with different architecture are designed to produce the effectual results. The lower order 4:2 Compressor is the mostly utilized for multipliers actualization founded on the less number of Transistors in place of conventional design. In the Arithmetic function nearly of design using Adders in a crucial portion. The design has to complete with the CMOS technology .The main purpose of this paper to reduce power consumption and delay in the 4:2 Compressor circuits using Adders.