Reducing Soft Errors in Register File by using Self-Immunity Technique

With the scaling of technology, Transient errors caused by external particle strikes have become a critical challenge for microprocessor design. As embedded processors are widely used in reliability-sensitive environments. It becomes important to develop the cost-effective techniques to improve the processor reliability against soft errors. This paper focuses on studying the register file immunity against soft errors. Register file is one of the essential architecture element. where soft errors can be very harmful because errors may spread from there throughout the whole system. This paper addresses a novel technique called Self-Immunity that improves the integrity of the register file against soft errors. Certain number of register bits are not always used to represent a value stored in a register. This paper deals with the difficulty to exploit obvious observation to enhance the register file integrity against soft errors. The Self-Immunity technique can reduce the vulnerability of the register file in terms of area and power overheads.