An Improved Cellular Automata-Based Multi Byte ECC

This paper identifies and resolves the weakness and limitation of existing Cellular Automata (CA)-based byte Error Correcting Code (ECC) and proposes an improved CA-based multi byte ECC which overcomes the identified weakness up to some extent. The code is very much suited from VLSI design viewpoint and requires significantly less hardware and power for decoding compared to the existing techniques employed for Reed–Solomon (RS) Codes. In this paper we are designing the Cellular Automata (CA) based multi byte error correction architecture. Cellular Automata is established for developing bits and bytes Error Correcting Codes. This code is very much suited from Very Large Scale Integration design viewpoint and requires much less hardware and power for decoding. The existing CA based error correcting scheme explains only about the double byte error correction. But this paper explains the error correction possibilities even if more than two errors present.