A Novel VLSI Architecture with Reduced Hard Multiple Based on Higher Radix Hybrid Modified Booth Algorithm

Hard multiple is the holdup process in higher radix Booth encoded multipliers. In this paper, a High-Level Design approach for the reduction of higher radix hard multiples is proposed. The method is used to optimize and re-design the internal algorithm and architecture of a low power multiplier with high-level design techniques. It can be achieved by a low-power Hybrid Multiplier using Modified Booth Encoder (MBE) by altering its basic Encoding scheme. In this Hybrid technique, Radix-4 (3-Bit) recoding and Radix-8 (4-Bit) encoding schemes are included in Radix-16 (5-Bit) recoding scheme. Synthesis results based on SDK 90nm, 1.32V CMOS standard-cell library shows that the proposed Hybrid multiplier reduces the power consumption by 20-25%.