Comparative Analysis of Low-Power High Speed Adder Cells

In this paper, techniques to build 1-bit full adders using less number of transistors are proposed. New design methodologies for the implementation of XOR and XNOR gates,which are the key components for full adder designs are presented here. This paper discusses two design methodologies for XOR and XNOR gates i.e. 3-T XOR and XNOR gates and Gate-Diffusion-Input (GDI) based XOR and XNOR gates. Two types of full adders are designed, 8-T full adders using 3-T XOR and XNOR gates and 10-T GDI based full adders. The adders are designed using low power technology. Almost all the new proposed adders consume less power as compared to the previously existing full adders due to lesser transistor count and their special structure. They also give improved performance in terms of delay and Power-Delay-Product (PDP), the deciding factors for efficiency measurement of the circuits.