A Review on Low Power Design Techniques of Flip-Flop

In past low power design techniques were not primary constraint because device density and operating frequency were low. Nowadays because of very large scale integration, millions of transistors are fabricated on a single chip and requirement of high performance, portable, battery based devices causes need of low power design techniques. Digital circuits are two types: combinational circuit and sequential circuit. Sequential circuit mainly consists of flip-flops. Flip-flop is basic storage element and consume large amount of power because they are clocked with system operating frequency.  Clock system consists of clock distribution network and flip-flops are most power consuming subsystems. Because of continuous increase in chip complexity and operating frequency reduction of power is long-winded task. After studying various journals and conferences, in this paper various low power Flip-flop design techniques are presented.