Design of Energy Efficient Approximate Multipliers for Image Processing Applications

This research paper presents the design of two 8×8 approximate multipliers based on novel approximate 3:2 and 2:2 compressors. The proposed multipliers are derived based on Wallace multiplier architecture and herein referred to as the proposed ‘approximate Wallace multiplier’ (AWM). The performance of these proposed AWMs has been assessed and analyzed in terms of ‘Design Metrics’ (DMs) such as power, delay, ‘power-delay-product’ (PDP), and area. Further, a performance comparison of AWMs has been carried out against 6 other multipliers designed based on reported approximate 3:2 compressors. To extract these DMs, all the multipliers under consideration have been described using Verilog code and synthesized using Cadence’s ‘RTL Compiler’ (RC) tool using a 180 nm standard cell library. The synthesis results show that the proposed AWMs accomplish an excellent performance in terms of DMs. Further, the AWMs along with other designed Wallace multipliers, based on reported approximate compressors have been compared, under image processing application in terms of ‘peak signal-to-noise ratio’ (PSNR). The comparison results show that the proposed multipliers have a better PSNR (more than 50 dB).