Power Research

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Admittance based algorithm of dynamic voltage restorer for improved power quality


Affiliations
1 Department of Electrical and Electronics Engineering, Stanley College of Engineering and Technology for Women, Abids, Hyderabad – 500001, India
2 Department of Electrical Engineering, S. V. National Institute of Technology, Surat-395007, India
3 Department of Electrical and Electronics Engineering, B V Raju Institute of Technology, Narsapur, Medak-502313, India
     

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This study deals with the admittance estimation algorithm for DVR for improvement of PQ in PDS (Power Distribution System). This admittance estimation algorithm based DVR is simple and easy to implement in simulation/hardware. In this admittance estimation algorithm, the estimation of active/reactive power components of load voltages are based on unit vectors in time domain and Low-Pass Filter (LPF). The mathematical analysis is easy, accurate and is used for fast estimation of reference load voltages using proposed algorithm. A three phase DVR using admittance estimation algorithm is modeled and implemented on real time hardware under balanced/unbalanced voltage sag, balanced/unbalanced voltage swell and harmonics compensation using Real Time Hardware Simulation and MATLAB under Simulink. Performance of admittance estimation algorithm for DVR in PDS shows quite satisfactory results using RT-LAB and MATLAB for the above power quality problems as per IEC and IEEE standards.

Keywords

DVR, harmonics, admittance estimation algorithm, voltage sag/swell, distribution System
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  • Admittance based algorithm of dynamic voltage restorer for improved power quality

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Authors

V. Rajagopal
Department of Electrical and Electronics Engineering, Stanley College of Engineering and Technology for Women, Abids, Hyderabad – 500001, India
Sabha Raj Arya
Department of Electrical Engineering, S. V. National Institute of Technology, Surat-395007, India
J. Bangarraju
Department of Electrical and Electronics Engineering, B V Raju Institute of Technology, Narsapur, Medak-502313, India
Sanjay K. Patel
Department of Electrical Engineering, S. V. National Institute of Technology, Surat-395007, India
V. Nagamalleswari
Department of Electrical and Electronics Engineering, Stanley College of Engineering and Technology for Women, Abids, Hyderabad – 500001, India

Abstract


This study deals with the admittance estimation algorithm for DVR for improvement of PQ in PDS (Power Distribution System). This admittance estimation algorithm based DVR is simple and easy to implement in simulation/hardware. In this admittance estimation algorithm, the estimation of active/reactive power components of load voltages are based on unit vectors in time domain and Low-Pass Filter (LPF). The mathematical analysis is easy, accurate and is used for fast estimation of reference load voltages using proposed algorithm. A three phase DVR using admittance estimation algorithm is modeled and implemented on real time hardware under balanced/unbalanced voltage sag, balanced/unbalanced voltage swell and harmonics compensation using Real Time Hardware Simulation and MATLAB under Simulink. Performance of admittance estimation algorithm for DVR in PDS shows quite satisfactory results using RT-LAB and MATLAB for the above power quality problems as per IEC and IEEE standards.

Keywords


DVR, harmonics, admittance estimation algorithm, voltage sag/swell, distribution System



DOI: https://doi.org/10.33686/prj.v13i2.189265