Modeling and Analyzing Cache for Multi-Core Processor

Ram Prasad Mohanty; Ashok Kumar Turuk; Bibhudatta Sahoo

Modeling and Analyzing Cache for Multi-Core Processor

Ram Prasad Mohanty ¹, Ashok Kumar Turuk ², Bibhudatta Sahoo ³

Affiliations
1 National Institute of Technology, Rourkela, Odisha, India
2 Department of Computer Science, National Institute of Technology, Rourkela, Odisha-769008, India
3 Computer Science Engineering Department, National Institute of Technology, Rourkela, Odisha-769008, India

The growing number of cores increases the demand for a powerful memory subsystem. This lead to enhancement in the size of caches in multi-core processors. Caches are responsible in giving processing elements a faster, higher bandwidth local memory to work with. In this paper, an attempt has been made to analyze the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on NIAGRA architecture. The SPLASH-2 benchmark has been used with the simulator Multi2Sim for these experimentations.