Power-Delay Co-Analysis of TSV for Three Dimensional Integrated Circuits

In this paper, the operation of S-G pair TSV, coaxial TSV, tapered S-G pair TSV and tapered coaxial TSV are analyzed where the TSV resistance, inductance, and capacitance need to be modeled to find out their impact on the performance of a 3-D circuit. The RLC parameters of the TSV are modeled as a function of physical factor and material characteristics. The performance of the analytically modeled TSV in the form of lumped elements (R, L, and C) circuit was simulated using the Virtuoso Schematic editor and Analog Design Environment of Cadence Tool. Delay, crosstalk and power are determined and compared between various TSV structures. The delay and power have been reduced in tapered coaxial TSV structure compared with other types of TSV structure.