High Speed CMOS Differential Logic Design for Carry Lookahead Adder

Growing need for portable devices has provoked ever increasing concern on energy efficient design. Since the energy consumption of modern digital CMOS circuits has been traditionally dominated by switching energy having quadratic dependence on supply voltage, voltage scaling is an effective way to minimize the overall energy consumption of system-on- chip. This brief describes a novel low-voltage CMOS differential logic operating with supply voltage approaching the MOS threshold voltage. The proposed logic style improves switching speed by boosting the gate–source voltage of transistors along timing-critical signal paths. The logic style also minimizes area overhead by allowing a single boosting circuit to be shared by complementary outputs. Test sets of logic gates were designed in a 0.18-μm CMOS process, whose comparison results indicated that the energy–delay product of the proposed logic style was improved by up to 86% compared with conventional logic styles at supply voltage ranging from 0.4 to 1.2 V. The experimental result for a 4-bit adder designed using the Microwind tool shows that proposed carry lookahead adder results in low power consumption compared to ripple carry adder, 64-bit adder design can be implemented in VHDL and synthesized using the proposed logic style based Xilinx ISE with an addition time of 4.8 ns at 0.5- supply, energy 31 pJ at 100 MHz.