Radix-4 Multiplier Design Using a Modified Pass-Transistor Logic Technique

Multiplication is one of the most important functions in arithmetic operations. A 1-bit adder is designed using the modified complementary pass transistor logic technique. The proposed adder is implemented in 4 Χ 4 bit high radix multiplier circuit. The paper describes the proposed adder technique for obtaining high speed, lower area, less power dissipation and lower propagation delay. The multiplier circuits were schematized using the DSCH2 Design Tool. Two unsigned multipliers were designed using the proposed modified complementary pass-transistor logic (CPL) adder cell, namely a Carry Save Array multiplier (CSA multiplier) and a Baugh-Wooley multiplier, for comparison with the proposed adder cell-based high radix multiplier. The proposed adder cell-based CSA multiplier and Baugh-Wooley multiplier are compared with the high radix multiplier circuit in terms of power dissipation, propagation delay and area. The proposed 1-bit adder and adder-based high radix multiplier demonstrates better performance than other two high speed multipliers. Proposed adder-based radix-4 multiplier can be used in DSP applications because it gives better performance than the Baugh-Wooley multiplier and CSA multiplier such as power dissipation, propagation delay and area.