Design and Analysis of N-Type CNTFET Single Edge Triggered D Flip-Flop Based Shift Registers

This paper enumerates the efficient design and analysis of shift registers like Serial in serial out (SISO), Serial in Parallel out (SIPO), Parallel in parallel out (PIPO), Parallel in serial out (PISO) using N-type CNTFET Single Edge Triggered D Flip-flop. The Flip flop is designed using Ballistic CNTFET (VHDL-AMS model) with the diameter of cnt is 1nm in resistive load inverter logic. There are many issues facing while integrating many number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by considering the carbon nano tube have promising application in the field of electronics. The transient and power analysis are obtained with operating voltage at 0.6V for the single edge triggered D flip-flop and shift registers using system vision tool. The simulation results are presented, and the power consumptions are compared with the conventional MOSFET design. The power consumption of D-Flipflop using mosfet has 9.136uw, whereas for the cntfet based design it was obtained as 0.15uw. Similarly when the shift registers were designed using cntfet power consumption values are 60% better than that of mosfet designs. The comparison of results indicated that the CNTFET based design is capable of efficient power savings.