Review of Multi-Bit Flip Flop Technique

Enhancement for power is one of the most important elements in modern Integrated Circuits (ICs) design [10]. However, the major part of power is consumed by the clock network generally dominates the dynamic power of the chip due to its most important Switching rate. Data-Driven Clock-Gating (DDCG) and Multi-Bit Flip-Flops (MBFFs) in which several FFs are clustered and share mutual clock driver are two effective low power design technique which is commonly used by VLSI designer [9]. In this project, present reduce the clock power consumption by using the Multi-Bit Flip-Flops (MBFFs) technique for the sequential circuits. Also, present the benefits of applying to merge 1-bit flip-flops into some multi-bit flip-flop for clock power saving. This paper is focused on various low power techniques. The multi-bit flip-flop is used to reduce the dynamic clock power Technique of multi-bit flip-flops are studied and discuss hears. An algorithm used to find out mergeable flip-flop are also discussed. It is observed that multi-bit flip-flop techniques are suitable for dynamic clock power reduction. The 8.1 % and 12.1 % improvement in dynamic power reduction has been observed in a case of M-Bit FF implementation over the conventional approach.