AES Implementation on FPGA

Cryptanalysis of symmetric and asymmetric ciphers is computationally extremely demanding. Since the security parameters of almost all practical crypto algorithms are chosen such that attacks with conventional computers are computationally infeasible. The DES algorithm is the most widely used private-key encryption algorithm. DES is a block cipher, which takes 64-bit input and 64-bit key. Since DES is easily breakable, the advanced version of DES namely Advanced Encryption Standard (AES) is used for implementation. The data block length is 128-bits and the key length may be 128-bits, 192-bits and 256- bits. In this paper, AES algorithm is implemented in Field Programmable Gate Arrays [FPGA] for optimizing area. Two architectures of AES are compared here. In one architecture, look-up-table method of s-box and general mix-column architecture are used and in other composite field arithmetic method of s-box and light weight mix-column architecture are used.